By replacing standard flip-flops with "Scan Flip-Flops," engineers can daisy-chain them into a long shift register. This allows you to "shift in" a specific state and "shift out" the result.
The fundamental dilemma is that normal functional operation and testing mode have contradictory requirements. Functionality seeks to minimise pins, hide internal states, and optimise speed. Testing seeks maximum access, full visibility, and deterministic control.
| Technique | Area Overhead | Test Time | Fault Coverage | In-Field Test | Complexity | | :--- | :--- | :--- | :--- | :--- | :--- | | Full Scan + ATPG | Medium (5-10%) | Medium | Excellent (>99%) | No | Medium | | Compressed Scan | Low (due to fewer pins) | Low (fast) | Excellent | No | High (added logic) | | Boundary Scan | Low (per I/O) | High (serial) | N/A (interconnects) | No | Low (standard) | | MBIST | Medium (per memory) | Low (parallel) | Excellent for memory | Yes | Medium | | LBIST | Medium (LFSR+MISR) | Medium | Good (90-95%) | Yes | High |
Used for random logic. While LBIST requires no external tester (only an on-chip clock and power), its fault coverage is typically lower than scan-based ATPG because pseudo-random patterns may miss certain faults. It is, however, perfect for in-field test and automotive safety (periodic self-test during operation). digital systems testing and testable design solution
Each embedded core within an SoC presents unique test requirements. The IEEE 1500 standard defines a wrapper architecture that isolates each core, providing standardized test access without exposing internal details. A then routes test data from chip pins to individual cores through a dedicated test bus. TAM design involves critical trade-offs: wider test buses reduce test time but consume more routing resources.
A Test Pattern Generator (TPG), often using a Linear Feedback Shift Register (LFSR), sends pseudorandom patterns through the logic. A Signature Analyzer then compresses the output responses.
Applying these patterns to physical silicon on automatic test equipment (ATE) to separate good chips from bad. 2. Testable Design Solutions: Design for Testability (DFT) Functionality seeks to minimise pins, hide internal states,
Physical defects are highly unpredictable. To analyze them mathematically, engineers map physical flaws to abstract representations called fault models. The Stuck-At Fault Model (SAF)
For critical or embedded systems (like memory cores or automotive ICs), external testers become impractical. BIST embeds the test logic directly on the chip. A Linear Feedback Shift Register (LFSR) generates pseudo-random test patterns, while a Multiple Input Signature Register (MISR) compresses the output responses into a unique "signature." If the signature matches the golden value, the circuit is fault-free. BIST allows a chip to test itself at power-up or during mission mode—a vital feature for avionics or medical implants.
For smaller, less critical designs, simple ad-hoc techniques provide immediate relief: While LBIST requires no external tester (only an
With clock frequencies exceeding 2-5 GHz, timing faults are as critical as stuck-at faults. is used:
If the actual output equals the expected output, the circuit passes. If not, a fault is detected. However, this simple definition belies a monumental challenge: is mathematically impossible for modern chips.
Implementing advanced DFT solutions is not without compromise. Engineers must carefully balance the benefits of high fault coverage against several distinct design costs: DFT Trade-off Metric Description Impact on Design